Testing & sorting
Sorted to ±5%. Logged 100%.
Cell makers ship LIC supercapacitor cells with capacitance tolerances as wide as −10/+30%. In a sixteen-cell series string that spread would push one cell toward its voltage ceiling while another idles well under its rating — the module would only ever be as good as its worst pairing. CapStack's line measures capacitance and ESR on every incoming cell and converges that −10/+30% spread into ±5% matched sets before a single busbar is welded.
Then the finished module has to prove itself: dielectric, telemetry, dormancy, surge — and a test report goes in the box.
The gate list
Twelve checks between cell and box
Methods follow IEC 62391; the gates are ours. Anything that misses a gate is binned out — never shipped inside a module. The table is the actual sequence a unit passes on the floor.
| Test item | Method / condition | Gate |
|---|---|---|
| Capacitance (DC) | IEC 62391 discharge method at 25 °C | Binned into ±5% sets from the −10/+30% raw spread |
| ESR (DC) | Measured together with capacitance, dual-parameter | Matched within the bin, not merely recorded |
| Leakage current | Held at rated voltage after full charge | Within cell datasheet limit |
| Self-discharge | 72 h open-circuit rest | ≥3.7 V retained at cell level |
| Temperature characterization | Chamber sweep across the −40…+70 °C series rating | Capacitance and ESR drift within limits |
| Dielectric withstand | AC 2,000 V for 1 minute, module level | No breakdown, no tracking |
| Insulation check | Clearance and creepage verified before powered tests | Pass before hi-pot and function |
| Balancing function | Cells deliberately offset, module powered | String auto-rebalances, module-to-module |
| Telemetry readback | CAN 2.0B frames polled on high-voltage versions | Per-cell voltage + NTC temperature reported correctly |
| Alarm logic | Over-charge / over-discharge / over-temperature injected | Three-level alarms plus error output asserted |
| Dormancy current | Module placed in sleep state | Draw below 20 µA |
| Surge pulse | >500 A-class pulse, under 5 s | No damage, parameters in spec |
The sorting floor
Where −10/+30% becomes ±5%
The sorting cabinet is where module quality is actually decided. Automated fixtures charge, rest and discharge each cell, compute capacitance and DC ESR, and drop the cell into a bin. Matched sets are then pulled from adjacent bins so that a 48 V module's sixteen cells sit inside a ±5% window on both parameters at once — capacitance and ESR together, because a capacity match with an ESR mismatch still runs hot at 130 A continuous.
Every measurement is logged against the cell serial. The report that ships with the module is therefore a record of real cells, not a promise about an average.
What ships with the module
Paper trail, in the box
Report
Per-module test report
Capacitance, ESR and the serial number of every cell inside that specific module — the document an integrator files at acceptance, not a marketing sheet.
Traceability
100% cell traceability
From incoming cell lot to welded module, every cell is logged. A field question five years into service gets a same-day answer from the archive.
Methods
IEC 62391 methods
Reports reference the standard's test methods, so submittals line up with what auditors, utilities and rack-integrator quality teams expect to see.
Proof over promises
Ask for the test report before you buy the module.
Sample orders move in 4–6 weeks with full data attached; volume follows the same gates. Describe the application and the numbers come back within 48 hours.
