Capacitance and ESR binning, explained

One string, one current, sixteen voltages

A 48.6 V module is sixteen LIC cells in series, welded into one string. Series means one thing above all: every cell carries exactly the same current and stores exactly the same charge, whether it wants to or not. Charge is shared equally because physics says so; voltage is not. Voltage divides in inverse proportion to capacitance, so the cell that stores least ends up holding the highest voltage.

Cell makers ship LIC cells with a capacitance tolerance as wide as −10/+30%. That is a normal manufacturing distribution, not a defect — but it means two cells from the same carton can differ by a third of their rated capacitance, and a string built straight from the carton divides voltage very unevenly indeed. Binning exists to close that gap before the first busbar is welded, and the target our line works to is ±5% on capacitance and ESR together.

The mismatch arithmetic, done properly

Take a sixteen-cell string charged to 16 × 3.8 V = 60.8 V, with one cell 5% low on capacitance and the other fifteen at nominal. The charge in the string is set by the sum of the reciprocal capacitances, and the weak cell takes a larger share of the total voltage:

• Sum of reciprocal capacitances: 1/0.95 + 15/1.00 = 16.05 (in units of 1/C₀)
• Charge per cell: 60.8 V ÷ 16.05 ≈ 3.79 C₀
• Voltage on the weak cell: 3.79 ÷ 0.95 ≈ 3.99 V
• Voltage on the other fifteen: ≈ 3.79 V

A single −5% cell consumes the entire 3.8 → 4.0 V headroom. Now run the full ±5% spread, one cell low and one high: the string spans roughly 3.62 V to 4.00 V at the same total voltage. Push that to ±10% and the low cell is driven to about 4.22 V before the string even reaches its nominal average — past the cell ceiling, which is why an unsorted string either alarms out early or has to be charged to a lower average voltage and quietly gives up usable energy. That is the whole argument for binning in two lines of arithmetic: the tolerance you accept in cells becomes the headroom you lose in the module.

ESR mismatch is the one that bites under load

Capacitance mismatch shows up as a voltage spread. ESR mismatch shows up as heat, and heat is what ages a capacitor. Large-format LIC cells run from 0.47 mΩ DC, so the arithmetic is easy to run at the module's own ratings. At 130 A continuous, one cell at 0.47 mΩ dissipates I²R = 130² × 0.00047 ≈ 7.9 W. Sixteen of them put roughly 127 W into a module that is cooled by natural air, which is why the continuous rating is a thermal rating as much as an electrical one.

Now give one cell 20% more ESR than its neighbours. It burns about 9.5 W where the others burn 7.9 W — a hot spot of 1.6 W inside a welded string, sitting at the same temperature as everything around it and aging faster for it. Push the same string into a surge above 500 A for a sub-5 s event and the per-cell dissipation passes 100 W, which is precisely why that surge class is time-limited. ESR binning is what keeps that surge heat shared evenly instead of concentrated in the cells that were already weakest.

There is a second consequence that matters to the system designer: string ESR adds up. Sixteen cells at 0.47 mΩ is about 7.5 mΩ before weld and busbar contributions, and at 500 A that is nearly 3.8 V of sag on a 48.6 V bus. A 20% ESR mismatch on one cell moves that number, and a moved number is a floor voltage you did not plan for. Binning to ±5% on ESR keeps the predicted string resistance — the figure your floor voltage and your protection thresholds are built on — honest.

How the two measurements are actually taken

Capacitance and ESR are not read off a nameplate; they are measured on every cell that enters the line. The methods follow IEC 62391: the cell is charged to its rated voltage, rested so the dielectric settles, then discharged through a known circuit while voltage and time are logged. Capacitance comes from the discharge slope, and DC ESR comes from the voltage step at the instant the discharge current starts — the resistive discontinuity, not the electrochemical response behind it. Four-terminal (Kelvin) connections are used so that fixture and cable resistance never lands in the cell's number.

Two details decide whether the data is worth anything. The first is temperature: measurements are taken at a controlled 25 °C, because a cell measured warm reads low ESR and a cell measured cold reads high, and a bin built from mixed temperatures is not a bin. The second is settling: a cell pulled straight off a charge reads optimistically, so every measurement follows the same charge-rest-discharge sequence. Identical handling for every cell is what makes the bins comparable — and comparability is the product being sold. The testing and sorting page lists the full gate set on our line.

Two-dimensional binning on the line

A bin is a box in a two-dimensional grid: one axis capacitance, one axis ESR. Sorting on capacitance alone is the classic mistake, because a capacitance match with an ESR mismatch still puts unequal heat into a welded string at 130 A. On our line every incoming cell is measured on both parameters at once, dropped into a two-dimensional bin, and matched sets are then pulled from a single bin so a sixteen-cell string comes from one box of the grid rather than a diagonal across it.

Tight bins cost yield, and it is worth saying so plainly. Converging a −10/+30% incoming spread into ±5% matched sets means some cells are reallocated to products whose current duty is gentler, and a few are set aside. That is a real cost inside the module price, and it buys a real property: a string whose cells all reach their voltage ceiling at the same moment, and whose heat is spread evenly across sixteen welds.

What a test report should show

Binning is only worth something if it is documented per unit. The report that ships with every module should let a reviewer answer three questions: which cells are in this box, what were they measured at, and what does the finished module measure. If a report cannot answer all three, it is a certificate of effort rather than a record of a product.

Note the word per unit. A report generated once for a design and copied into cartons tells you nothing about the cells in your rack. Our line tests 100% of modules, not a sample, and logs the result against the serial number — the same serial that appears on the carton.

How to audit a binning claim

Binning sits upstream of everything a buyer can see, which makes it a claim worth testing rather than trusting. Four questions separate a real sorting line from a marketing line.

• Ask for the raw distribution. What is the incoming cell spread, and what does the bin occupancy look like over a month? A supplier who sorts has this data; one who does not has a brochure.
• Ask for serial-level data on a delivered unit. Pick a module serial from your last shipment and request the cell list behind it. If it takes a week, traceability is a slogan.
• Re-measure on arrival. Pull a sample module at incoming inspection and measure string capacitance and DC ESR against the report. Small differences are measurement noise; a systematic offset is a process problem.
• Ask what happens to the outliers. The answer tells you whether ±5% is a shipping window or an aspiration. Ours is that C-bin cells never enter a shipped module.

Binning is the least glamorous step between a cell and a rack, and it is the one that decides whether the module in your third year of service behaves like the module in your first. Ask for the paperwork that proves it — and if the voltage window in your design is unusually wide, the same sorted cells feed the 16–108 V custom builds so the argument holds at any series count.